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LH532000B-1
FEATURES * 262,144 words x 8 bit organization (Byte mode) 131,072 words x 16 bit organization (Word mode) * Access time: 120 ns (MAX.) * Power consumption: Operating: 275 mW (MAX.) Standby: 550 W (MAX.) * Mask-programmable control pin (for 40-pin DIP/40-pin SOP): Pin 1 = OE1/OE1/DC Pin 12 = OE/OE * Static operation * TTL compatible I/O * Three-state outputs * Single +5 V power supply * Packages: 40-pin, 600-mil DIP 40-pin, 525-mil SOP 48-pin, 12 x 18 mm2 TSOP (Type I) DESCRIPTION
The LH532000B-1 is a CMOS 2M-bit mask-programmable ROM organized as 262,144 x 8 bits (Byte mode) or 131,072 x 16 bits (Word mode) that can be selected by BYTE input pin. It is fabricated using silicon-gate CMOS process technology.
CMOS 2M (256K x 8/128K x 16) MROM
PIN CONNECTIONS
40-PIN DIP 40-PIN SOP TOP VIEW
OE1/OE1/DC A7 A6 A5 A4 A3 A2 A1 A0 CE GND OE/OE D0 D8 D1 D9 D2 D10 D3 D11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE GND D15/A-1 D7 D14 D6 D13 D5 D12 D4 VCC
532000B1-1
Figure 1. Pin Connections for DIP and SOP Packages
1
LH532000B-1
CMOS 2M MROM
48-PIN TSOP (Type I)
TOP VIEW
BYTE A16 A15 A14 A13 A12 A11 A10 A9 A8 NC GND NC NC OE1/OE1/DC A7 A6 A5 A4 A3 A2 A1 A0 CE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
GND GND D15/A-1 D7 D14 D6 D13 D5 D12 D4 VCC VCC GND D11 D3 D10 D2 D9 D1 D8 D0 OE/OE GND GND
NOTE: Reverse bend available on request.
532000B1-2
Figure 2. Pin Connections for TSOP Package
2
CMOS 2M MROM
LH532000B-1
A16 32 A15 33 A14 34
ADDRESS DECODER
A10 38 A9 39 A8 40 A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 A0 9
ADDRESS BUFFER
A13 35 A12 36 A11 37
MEMORY MATRIX (262,144 x 8 ) (131,072 x 16 )
COLUMN SELECTOR
SENSE AMPLIFIER
CE 10
CE BUFFER
TIMING GENERATOR
OE/OE 12 OE1/OE1/DC 1
OE BUFFER
DATA SELECTOR/OUTPUT BUFFER
BYTE 31
BYTE/WORD SWITCHOVER CIRCUIT
ADDRESS BUFFER
21 VCC
11 GND
30 GND
29 A-1
13 15 17 19 22 24 26 28 14 16 18 20 23 25 27 29 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
532000B1-3
NOTE: Pin numbers apply to 40-pin DIP or SOP.
Figure 3. LH532000B-1 Block Diagram
PIN DESCRIPTION
SIGNAL PIN NAME NOTE SIGNAL PIN NAME NOTE
A-1 - A16 D0 - D15 BYTE CE
Address input Data output Byte/word mode switch Chip enable input
1 1 1
OE/OE OE1/OE1/DC VCC GND
Output enable input Output enable input Power supply (+5 V) Ground
2 2
NOTES: 1. D15/A-1 pin becomes LSB address input (A-1) when the BYTE pin is set to be LOW in byte mode, and data output (D15) when set to be HIGH in word mode. 2. The active levels of OE/OE and OE1/OE1/DC are mask-programmable.
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LH532000B-1
CMOS 2M MROM
TRUTH TABLE
CE OE/OE OE1/OE1 BYTE A-1 (D15) DATA OUTPUT D0 - D7 D8 - D15 ADDRESS INPUT LSB MSB SUPPLY CURRENT
H L L L L L
NOTE: 1. X = H or L.
X L/H X H/L H/L H/L
X X L/H H/L H/L H/L
X X X H L L
X X X - L H
High-Z High-Z High-Z D0 - D7 D0 - D7 D8 - D15
High-Z High-Z High-Z D8 - D15 High-Z High-Z
- - - A0 A-1 A-1
- - - A16 A16 A16
Standby (ISB) Operating (ICC) Operating (ICC) Operating (ICC) Operating (ICC) Operating (ICC)
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT
Supply voltage Input voltage Output voltage Operating temperature Storage temperature
VCC VIN VOUT Topr Tstg
- 0.3 to +7.0 - 0.3 to VCC + 0.3 - 0.3 to VCC + 0.3 0 to +70 - 65 to +150
V V V C C
RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Supply voltage
VCC
4.5
5.0
5.5
V
DC CHARACTERISTICS (VCC = 5 V 10%, TA = 0 to +70C)
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE
Input `Low' voltage Input `High' voltage Output `Low' voltage Output `High' voltage Input leakage current Output leakage current
VIL V IH VOL VOH | ILI | | ILO | ICC1 ICC2 ICC3 ICC4 ISB1 ISB2 CIN COUT I OL = 2.0 mA I OH = -400 A V IN = 0 V to VCC V OUT = 0 V to VCC t RC = 120 ns t RC = 1 s t RC = 120 ns t RC = 1 s CE = VIH CE = VCC - 0.2 V f = 1 MHz T A = 25C
- 0.3 2.2 2.4
0.8 VCC + 0.3 0.4 10 10 50 45 45 40 3 100 10 10
V V V V A A mA mA mA mA mA A pF pF 1 2 2 3 3
Operating current
Standby current Input capacitance Output capacitance
NOTES: 1. CE/OE/OE1 = VIH, OE/OE1 = VIL 2. VIN = VIH or VIL, CE = VIL, outputs open 3. VIN = (VCC - 0.2 V) or 0.2 V, CE = 0.2 V, outputs open
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CMOS 2M MROM
LH532000B-1
AC CHARACTERISTICS (VCC = 5 V 10%, TA = 0 to +70C)
PARAMETER SYMBOL MIN. MAX. UNIT NOTE
Read cycle time Address access time Chip enable access time Output enable delay time Output hold time CE to output in High-Z OE to output in High-Z
tRC tAA tACE tOE tOH tCHZ tOHZ
120 120 120 55 5 55 55
ns ns ns ns ns ns ns 1
NOTE: 1. This is the time required for the output to become high-impedance.
AC TEST CONDITIONS
PARAMETER RATING
Input voltage amplitude Input rise/fall time Input reference level Output reference level Output load condition
0.6 V to 2.4 V 10 ns 1.5 V 0.8 V and 2.2 V 1 TTL + 100 pF
CAUTION
To stabilize the power supply, it is recommended that a high-frequency bypass capacitor be connected between the VCC pin and the GND pin.
5
LH532000B-1
CMOS 2M MROM
tRC
A-1 - A16 tAA (NOTE)
CE tACE (NOTE) OE/OE1 OE/OE1 tOE (NOTE) tOH tOHZ tCHZ
D0 - D7
DATA VALID
NOTE: The output data becomes valid when the last intervals, tAA, tACE, or tOE have concluded.
532000B1-4
Figure 4. Byte Mode (BYTE = VIL)
tRC
A0 - A16 tAA (NOTE)
CE tACE (NOTE) OE/OE1 OE/OE1 tOE (NOTE) tOH tOHZ tCHZ
D0 - D15
DATA VALID
NOTE: The output data becomes valid when the last intervals, tAA, tACE, or tOE have concluded.
532000B1-5
Figure 5. Word Mode (BYTE = VIH)
6
CMOS 2M MROM
LH532000B-1
PACKAGE DIAGRAMS
40DIP (DIP040-P-0600)
40 21
DETAIL
13.45 [0.530] 12.95 [0.510]
1 52.30 [2.059] 51.70 [2.035]
20
0 TO 15 0.30 [0.012] 0.20 [0.008]
4.55 [0.179] 3.95 [0.156] 5.40 [0.213] 4.80 [0.189] 3.55 [0.140] 2.95 [0.116] 2.54 [0.100] TYP. 0.51 [0.020] MIN. 0.60 [0.024] 0.40 [0.016] MAXIMUM LIMIT MINIMUM LIMIT
15.24 [0.600] TYP.
DIMENSIONS IN MM [INCHES]
40DIP
40-pin, 600-mil DIP
40SOP (SOP040-P-0525)
1.27 [0.050] TYP. 1.40 [0.055] 21
0.50 [0.020] 0.30 [0.012]
40
11.50 [0.453] 11.10 [0.437]
14.50 [0.571] 13.70 [0.539]
12.50 [0.492]
1 26.50 [1.043] 26.10 [1.028]
20 1.40 [0.055] 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.275 [0.050] 2.90 [0.114] 2.50 [0.098] 0.20 [0.008] 0.00 [0.000] 1.275 [0.050] MAXIMUM LIMIT MINIMUM LIMIT
DIMENSIONS IN MM [INCHES]
40SOP
40-pin, 525-mil SOP
7
LH532000B-1
CMOS 2M MROM
48TSOP (TSOP048-P-1218)
0.50 [0.020] TYP. 48 0.30 [0.012] 0.10 [0.004] 25
16.60 [0.654] 16.20 [0.638]
18.40 [0.724] 17.60 [0.693]
17.00 [0.669]
1 12.20 [0.480] 11.80 [0.465]
24 0.20 [0.008] 0.10 [0.004] 1.10 [0.043] 0.90 [0.035] 1.20 [0.047] MAX. 0.425 [0.017] 0.20 [0.008] 0.00 [0.000]
0.15 [0.006] 0.425 [0.017]
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT MINIMUM LIMIT
48TSOP
48-pin, 12 x 18 mm TSOP (Type I)
2
ORDERING INFORMATION
LH532000B Device Type X Package -1 120 ns Version
D N T TR
40-pin, 600-mil DIP (DIP040-P-0600) 40-pin, 525-mil SOP (SOP040-P-0525) 48-pin, 12 x 18 mm2 TSOP (Type I) (TSOP048-P-1218) 48-pin, 12 x 18 mm2 TSOP (Type I) Reverse bend (TSOP048-P-1218)
CMOS 2M (256K x 8 or 128K x 16) Mask-Programmable ROM Example: LH532000BD-1 (CMOS 2M (256K x 8 or 128K x 16) Mask-Programmable ROM, 40-pin, 600-mil DIP)
532000B1-6
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